1. Field of the Invention
The present invention relates to random access memories, and in particular relates to a method of adjusting read timing of random access memories.
2. Description of the Related Art
The access time of a random access memory (RAM) is a crucial factor for improving the performance and speed of an electronic system. The RAS (Row Address Strobe) to CAS (Column Address Strobe) latency is a delay time between an active command and a read command sent from a command decoder in a random access memory, and CAS (Column Address Strobe) latency is a delay time between the time the read command is sent and the time the memory data is ready to be read out at a data bus. After the read command is sent, a column select signal is subsequently (later than the read command being output for a predetermined time) output by a column enable circuit in the random access memory. In conventional art, the output timing of the column select signal is not flexible, thus missing an opportunity for improving operation of Read data-path transmission or operation of bit-line for the random access memory.